Various digital full adders have been proposed and implemented in arithmetic and logic circuits fabricated on semiconductor chips. However, larger integration and the improvement in processing speed is difficult to achieve when using the digital full adders due to technical problems associated with miniaturization of their component elements. For example, a signal propagation delay may be caused by a large parasitic capacitance coupled to each conductive wiring layer and a large area occupied by the wiring layers.
A multiple-valued arithmetic circuit implemented as an integrated circuit is proposed for not only providing a technical breakthrough but also avoiding the complex wiring arrangement. Each interconnecting wiring layer incorporated in the integrated circuit is available as a multiple-valued signal propagation path for the multiple-valued arithmetic circuit, and, for this reason, a relatively small area is occupied by the wiring layers. This results in enhancement in integration density. For example, Kawahito et al reported in Symposium on VLSI Technology held in 1987 that a 32.times.32 bit multiplier was implemented for processing radix-4 signed-digit numbers by using multiple-valued MOS current-mode circuits, the occupation area of which is a half of that of a known digital multiplier but the performance of which is equivalent to the known digital multiplier. This is because of the fact that each radix-4 full adder is capable of simultaneously processing two bits of each input data signal. Each full adder of the multiple-valued current-mode type is composed by 26 transistors, and each known digital full adder is formed by 9 NAND gates each consisting of three transistors. Then, the full adder of the multiple-valued current-mode type is not drastically decreased in the number of the component transistors. However, the full adder of the multiple-valued current-mode type is twice as large in the number of the simultaneously processed bits as the digital full adder. This is conducive to the enhancement of the integration density without increasing the occupation area.
In general, assuming now that two integers each ranging between zero and m-1 are supplied to a radix-m full adder where m is an integer not less than two and that a carry bit c' supplied from a lower bit is either one or zero, the sum s and the carry bit c are represented by the following equation EQU m.multidot.c+s=x+y+c' (Eq. 1)
where the sum s is an integer not less than zero and not greater than m-1 and the carry bit c is either zero or one.
In case of the binary operation or the m is equal to two, the sum s is achieved by exclusive OR operation. However, if the m is a multiple-valued integer, it is difficult to obtain the sum s by a simple logic operation. For this reason, the prior art full adder sequence is decreased in stage by increasing the value of the m, but each full adder is increased in circuit complexity. This trade-off causes a restriction on the improvement in operation speed and on the enhancement of the integration density, and, for this reason, a new approach is desired to improve the operation speed as well as the integration density.